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AR# 10068

SYNPLIFY - How do I use the INIT attribute to initialize a LUT in VHDL and Verilog?

Description

General Description:

When instantiating a LUT in VHDL, how do I use the INIT attribute to set the LUT equation?

Solution

The following file gives an example of how to use the INIT attribute to initialize the equation in the instantiated LUT. The specific device library must be included in order to reference the device-specific components in Synplify. In this case, the Virtex library was used; however, the examples will work for the Spartan-II and the Virtex-II architectures if the appropriate library is included.

Test case for using INIT attribute:

-- 4 input comparator with chip select example.

-- Given the signal DATA_IN (3 downto 0), the LUT equation is as follows:

~DATA_IN(3) * ~DATA_IN(2) * DATA_IN(1) * DATA_IN(0)

Library IEEE;

use IEEE.std_logic_1164.all;

library unisim;

use unisim.vcomponents.all;

entity muxtest is port (

DATA_IN : in std_logic_vector ( 3 downto 0 );

CS : in std_logic;

CLK : in std_logic;

DATA_OUT : out std_logic );

end muxtest;

architecture structural of muxtest is

component LUT4

generic (INIT : bit_vector (15 downto 0) := b"0000000000000000");

port (

I0 : in std_logic;

I1 : in std_logic;

I2 : in std_logic;

I3 : in std_logic;

O : out std_logic

);

end component;

component MUXF5

port (

I0 : in std_logic;

I1 : in std_logic;

S : in std_logic;

O : out std_logic

);

end component;

component GND

port(

G : out STD_ULOGIC );

end component;

signal LUT_OUT: std_logic;

signal MUX_OUT: std_logic;

signal GND_IN: std_logic;

begin

MYLUT1: LUT4

generic map (

INIT => b"0000_0000_0000_1000"

)

port map (

I0 => DATA_IN(0),

I1 => DATA_IN(1),

I2 => DATA_IN(2),

I3 => DATA_IN(3),

O => LUT_OUT

);

MYMUXF5: MUXF5 port map (

I0 => LUT_OUT,

I1 => GND_IN,

S => CS,

O => MUX_OUT

);

MYGND: GND port map ( G => GND_IN );

process ( CLK )

begin

if ( CLK = '1' and CLK'event ) then

DATA_OUT <= MUX_OUT;

end if;

end process;

end structural;

The following file gives an example of how to use the INIT attribute to initialize the equation in the instantiated LUT. The specific device library must be included in order to reference the device-specific components in Synplify. In this case, the Virtex library was used: however, the examples will work for the Spartan-II and the Virtex-II architectures if the appropriate library is included.

Test case for using INIT attribute:

-- 4 input comparator with chip select example.

-- Given the signal DATA_IN (3 downto 0), the LUT equation is as follows:

~data_in[3] * ~data_in[2] * data_in[1] * data_in[0]

`include "c:\synplicity\synplify\lib\xilinx\unisim.v"

module muxtest (data_in, cs, clk, data_out);

input [3:0] data_in;

input cs, clk;

output data_out;

wire lut_out, mux_out, gnd_in;

reg data_out;

// The #(16'h8) below will pass a hexadecimal value of '8'

// to the first paramter statement in the LUT4 definition

// found in the virtex.v file.

LUT4 #(16'h8) mylut1 (.I0(data_in[0]), .I1 (data_in[1]), .I2(data_in[2]), .I3(data_in[3]), .O(lut_out));

MUXF5 mymuxf5 (.I0(lut_out), .I1(gnd_in), .S(cs), .O(mux_out));

GND mygnd (.G(gnd_in));

always @(posedge clk) data_out <= mux_out;

endmodule

AR# 10068
Date Created 08/29/2007
Last Updated 12/15/2012
Status Active
Type General Article