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AR# 10069

4.1i Virtex/E Timing - The timing path is incorrect when I cascade DLLs for 4X clock multiplication


General Description:

When I perform a timing analysis of a path through two DLLs, the second DLL removes too much delay. This analysis indicates that the internal clock generated by the DLL arrives before the external clock sourcing the DLL. Why does this happen?


This is the result of the manner in which the timing tool models the DLL. In reality, the delay on this path would be closer to 0 ns. This problem only affects a case where two DLLs are cascaded together (for example, to create a 4X clock).

This issue was fixed in the 4.1i software.

AR# 10069
Date Created 08/29/2007
Last Updated 01/18/2010
Status Archive
Type General Article