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AR# 10080

3.1i XST - ERROR: (VLG__5002). filename Line #. Could not open include file '<filename>'


Keywords: include, file, Verilog, 5002

Urgency: Standard

General Description:
When synthesizing a Verilog design that has one or more `include statements, I encounter the following error message:

ERROR: (VLG__5002). <filename> Line #. Could not open include file '<filename>'


This problem occurs because XST is looking for the include files in the project directory. To avoid the error, copy all of the include files into the project directory.
AR# 10080
Date Created 09/01/2000
Last Updated 08/19/2002
Status Archive
Type General Article