We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 10130

6.1 System Generator for DSP - Can I generate Verilog HDL code?


Keywords: MathWorks, MATLAB, Simulink, SysGen, token

When I use the System Generator token to generate my Xilinx design, I see only VHDL code being generated. Can I generate Verilog code?


Starting with System Generator for DSP 6.3, you can now generate Verilog Code.

The System Generator for DSP Users Guide lists the limitations of Verilog Netlisting.
AR# 10130
Date Created 09/12/2000
Last Updated 07/18/2007
Status Archive
Type General Article