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AR# 10146

LogiCORE PCI - The IDSEL signal appears to be driven to only 1/2 the threshold voltage level that is required.


General Description:

The IDSEL signal appears to be driven to only 1/2 the

threshold voltage when viewed on an oscilloscope.


The IDSEL signal can be shared with the upper AD

lines on a PCI board. If the IDSEL signal is not

consistently reaching the necessary threshold voltage,

there may be contention on this signal and the shared

signal from the AD bus.

It is possible that the PCI core is actively driving the

AD bus at the same time that the host agent is asserting

the IDSEL signal.

The most common reason for this occurance is that the

GNT# signal is left unconnected (floating) either on the

board or inside the FPGA. If this signal floats to a LOW

state inside the FPGA, the PCI Core will enable the output

buffers for the AD, C/BE#, and PAR signals. This is

known as Bus Parking (PCI Specification, Rev 2.2).

If this is a target-only design, be sure that the GNT# line

is tied high through a resistor. Otherwise, make sure it is

connected between the PCI connector and the Xilinx FPGA.

AR# 10146
Date Created 08/29/2007
Last Updated 12/15/2012
Status Active
Type General Article