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AR# 10155

Virtex LogiCORE PCI - The PCI LogiCORE requests the PCI bus unexpectedly after the bus master control bit is set in the Configuration Space Header

Description

General Description:

The Virtex PCI LogiCORE unexpectedly asserts the REQ# signal after the bus master bit is set in the Command/Status register.

(The Command/Status register is located in the PCI Configuration Space Header.)

Solution

This will occur if the REQUEST user application signal is asserted before the bus master control bit is set. The Virtex PCI LogiCORE stores the most recent REQUEST from the user application after reset is de-asserted.

AR# 10155
Date Created 08/29/2007
Last Updated 12/15/2012
Status Active
Type General Article