We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Page Bookmarked

AR# 10156

3.1i SP2 Virtex-E PAR - PAR errors out on IBUFG_LVDS inputs for XCV405E


Keywords: LVDS, Virtex-E, V405E, IBUFG, clock, differential, 3.1, PAR, Place

Urgency: Hot

General Description:
Instantiation of the IBUFG_LVDS component for V405E-BG560 results in the following errors:

"ERROR:Place:1729 - The IOB component clkin has an IO standard of LVDS which
must be placed with locate constraints to specific IOB locations that support
this standard. The current location A17 is not a possible LVDS IOB location.
Refer to the application note for LVDS."

"ERROR:Place:1582 - The IOBs in your design cannot be automatically placed.
Xilinx recommends that you lock your IOBs to specific sites."

"ERROR:Place:993 - Due to Virtex SelectIO banking constraints, the IOBs in your
design cannot be automatically placed."


This problem is fixed in the latest 3.1i Service Pack available at:
AR# 10156
Date 10/14/2004
Status Archive
Type ??????