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AR# 1016

Using MakeTNM and addTNM in order to add TNMS to a .XNF file.


The MakeTNM and AddTNM programs allow the user to add TNMS
to a behavioral design. The user will then be able to define
some timespecs in a constraint file.


The latest versions of addtnm and maketnm are:

addtnm v.2.3.4
maketnm v2.3.3

The latest version of those two PERL scripts can be obtained
via the Xilinx FTP site in
/pub/swhelp/synopsys/addmaketnm.tar.Z or the Xilinx
BBS(408-559-9327) in \swhlp\synopsys\amtnm.zip.

Maketnm reads the .xff file and makes a template file (.tt)
listing all of the flip-flops, rams and pads in the design.
This file is then rename to a .tnm extension. Also, the user
needs to edit it and put each flip-flop, ram or pad in it's own
Wildcards can be used with the hierarchical names to make this
job a little less tedious.

Once this is done, run "maketnm design". This will read your
.xff and .tnm files, and put the "TNM=GROUP_NAME" attribute
onto each of the components listed in your .tnm file. The
output file from this script has a .txff extension. You then
need to change this to a .xff extension.

You then put the actual timing constraints into your .cst file
before running XNFPREP. If your design has X-BLOX components
(where XNFPREP is run twice), this timing information is only
looked at the *FIRST* time you run XNFPREP, so make sure the
FROM:TO groups are in the .cst file then.

This is then put into the .xtf/.xtg file, so by the time PPR gets it, all the Timespecs are in the file. After PPR runs, you
can check the .tsi file to see which paths are not spec'ed.

Since these are PERL scripts, you do need to get the perl
executable for the PC. Check the perl homepage at http://www.perl.com for more information.

Synopsys is very consistent about what it names flops, so from
one synthesis run to the next, the old .tnm file is usable.
Exemplar sometimes calls things "my_register8800" or some
logical name with an ill-logical number on it.
Hopefully, this number won't change with every new compilation.

Refer to the Reference Guide volume1 and the HDL Synthesis user
guide (p3-53) for further informations.
AR# 1016
Date Created 05/20/1996
Last Updated 03/19/2000
Status Archive
Type General Article