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AR# 1017

Designing with the XC5200 family using synthesis

Description

Here are some things to look for when designing with the XC5200 family
using synthesis :

Solution


* Arithmetic logic : This uses twice as many columns as the XC4000. If
you have a counter/incrementer that is loadable,
you can get it done with one less column if you
use XBLOXGEN and instantiate the resulting XNF file.

* Clock enables : Each CLB shares a dedicated clock enable. The more
clock enables you have, the harder it is for the
placer to put things in the same CLB. This spreads
the logic out, causing more nets and routing delays.

* Asynch resets : Same story as above.

* Horizontal LL : The more TBUFs you use, the more you restrict the
router. It's harder for the router to get across the
chip.
AR# 1017
Date Created 05/20/1996
Last Updated 10/14/2004
Status Archive
Type General Article