AR #10177 - ModelSim (MXE, SE, PE) - How do I run back-annotated (timing) simulation using ModelSim stand-alone? (VHDL, Verilog)

AR#	10177
Part	SW-3rd Party Sim Tool
Last Modified	2008-10-16 00:00:00.0
Status	Archive
Keywords	SDF, MTI

Solution

For information on running a functional simulation using ModelSim stand-alone, see (Xilinx Answer 1078).

Running Simulation from Project Navigator (VHDL or Verilog)

When running a simulation from Project Navigator, a timing simulation will run automatically. Select the Testbench in the Sources Window in Project Navigator, then run the Simulate Post Place & Route process in the Processes Window.

For additional information on how to run simulation from Project Navigator, see (Xilinx Answer 18216).

Verilog - Running MTI Stand-alone

1. If you have not compiled the Xilinx Simulation Libraries, see (Xilinx Answer 15338) for information on how to compile the libraries.

2. Create the Simulation Model.

Using Project Navigator:
Under each stage in the Implement Design process, there is a Generate Simulation Model Process. For instance, under the Place & Route process is the Generate Post-Place & Route Simulation Model. This will run the NetGen utility to generate a simulation model and an SDF file with the timing information. The default name of the model and the SDF file are "<design_name>_timesim.v" and "<design_name>_timesim.sdf." You can right-click the Simulate Process to change the properties for generating the model. Click Help for a description of each property.

Using Command Line:
NetGen is the executable that creates simulation models. See (Xilinx Answer 17883) for more information about NetGen.

NOTE: This step can be skipped if using ISE 8.1i and above
3. Compile the "glbl.v" module, the generated simulation model, and the testbench. For example:
vlog $env(XILINX)/verilog/src/glbl.v <design_name>_timesim.v <testbench>.v

For more information about the "glbl.v" module, see (Xilinx Answer 6537).

4. Load the design in ModelSim and use the -L switch to point to the Verilog SimPrim models that define the behavior of the components in the simulation model. The "glbl" needs to be loaded as well.
vsim -t ps -L simprims_ver work.<testbench> work.glbl

The SDF file with the timing information is automatically loaded. See (Xilinx Answer 10651) for more information.

NOTE: The "glbl.v" automatically pulses Global Set/Reset (GSR) for the first 100 ns of the simulation. See (Xilinx Answer 6537) for more information.

VHDL - Running MTI Stand-alone
1. If you have not compiled the Xilinx Simulation Libraries, see (Xilinx Answer 15338) for information on how to compile the libraries.

2. Create the Simulation Model

Using Project Navigator:
Under each stage in the Implement Design process, there is a Generate Simulation Model Process. For instance, under the Place & Route process is the Generate Post-Place & Route Simulation Model. This will run the NetGen utility to generate a simulation model and an SDF file with the timing information. The default name of the model and the SDF file are "<design_name>_timesim.vhd" and "<design_name>_timesim.sdf." You can right-click the Simulate Process to change the properties for generating the model. Click Help for a description of each property.

Using Command Line:
NetGen is the executable that creates simulation models. See (Xilinx Answer 17883) for more information about NetGen.

3. Compile the generated simulation model, and the testbench. For example:
vcom -93 <design_name>_timesim.vhd testbench.vhd

4. Load the design, including the SDF (Standard delay format) file:
vsim -t ps -sdfmax /UUT=<design_name>_timesim.sdf work.testbench
See (Xilinx Answer 10651) for additional information about loading the SDF file.

NOTE: The Global Set/Reset (GSR) is automatically pulsed for the first 100 ns of the simulation by the simulation model. See (Xilinx Answer 5009) for more information.