We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 10180

3.4 FPGA Express - FPGA Express does not export clock pin lock constraint for 4k architectures.


Keywords: pin, lock, constraint, clock, 4k

Urgency: Standard

General Description:
FPGA Express normally exports pin-locking information in the EDIF netlist.
However, FPGA Express does not export pin-locking information for clock
ports in 4K architectures.


Use a UCF to lock the clock pins. Below is an example of the appropriate
UCF syntax for the LOC constraint:

NET clock LOC=P57;
AR# 10180
Date Created 09/20/2000
Last Updated 08/28/2001
Status Archive
Type General Article