We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 10226

3.1i Foundation ISE - Addition of a VHDL or Verilog source causes Project Navigator to hang


Keywords: Project Navigator, ISE, hang, not respond, add

Urgency: Standard

General Description:
Adding a VHDL or Verilog source causes Project Navigator to hang, as in the
following example:

--synopsys translate_off

library unisims;
use unisims.all;

-- synopsys translate_on


This problem will be fixed in the next 3.1i Service Pack available at:
http://support.xilinx.com/support/techsup/sw_updates. The first
service pack containing the fix will be 3.1i Service Pack 4, due out in
October, 2000.
AR# 10226
Date Created 09/26/2000
Last Updated 01/15/2003
Status Archive
Type General Article