When the Xilinx PCI Core is the target of a configuration read or write,
it does not respond.
This may occur if the C_TERM and C_READY signals are either left
unconnected or are connected incorrectly. Please refer to chapter
16 of the LogiCORE PCI Design Guide for more information regarding
The LogiCORE PCI Design guide can be found in the docs directory
where the core is installed.