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AR# 10254

3.1i Virtex MAP - MAP produces a bad NGM file, affecting simulation results.


Keywords: simulation, NGM, LUT, constant, VCC, annotation, annotated

Urgency: Standard

General Description:
The EDIF netlist contains an all zero LUT. This appears to be optimized away and
replaced by a constant "1" in the generated VHD file.

This LUT is an XOR function with the I1 input tied low. In the generated .vhd file, this
is seen as VCC. When examined in FPGA Editor, everything seems correct -- this
indicates that only the back-annotated results are affected.


This problem is fixed in the latest 3.1i Service Pack available at:
http://support.xilinx.com/support/techsup/sw_updates. The first
service pack containing the fix is 3.1i Service Pack 4.
AR# 10254
Date Created 09/30/2000
Last Updated 08/19/2002
Status Archive
Type General Article