UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 10318

SIMPRIMS 3.1iSP4 - FACTORY_JF parameter causes simulation error in back-annotated (timing) simulation. (VHDL)

Description

Keywords: Factory_jf, simprims, X_CLKDLL2, timing, simulation,
modelsim, mti, verilog, vhdl, vcs, vss, verilog-xl

Urgency: Hot

General Description:
While running 3.1i with Service Pack 4, an invalid parameter (FACTORY_JF)
is being passed through NGD2VHDL/NGD2VER which causes an error during
timing simulation. The following error occurs in ModelSim:

ERROR: Unknown identifier: factory_jf.

Solution

A workaround for this problem is to comment out the line
containing FACTORY_JF in the back-annotated timing
netlist generated by Xilinx:

ERRONEOUS INSTANTIATION:
BCLK_DLL_OUT : X_CLKDLL2
generic map (
CLKDV_DIVIDE => 2.0,
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => X"C080", -- Comment out this line
MAXPERCLKIN => 40000 ps
)
port map (
RST => RESE.....

CORRECTED INSTANTIATION:
BCLK_DLL_OUT : X_CLKDLL2
generic map (
CLKDV_DIVIDE => 2.0,
DUTY_CYCLE_CORRECTION => TRUE,
-- FACTORY_JF => X"C080", -- This line is now commented out
MAXPERCLKIN => 40000 ps
)
port map (
RST => RESE.....

This problem will be fixed in the next 3.1i Service Pack, Service Pack 5,
which is due out in November, 2000.
AR# 10318
Date Created 10/12/2000
Last Updated 06/30/2004
Status Archive
Type General Article