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AR# 10330

3.1i COREGen - Virtex DP BlockRAM - RAM outputs are unknown at start of behavioral VHDL simulation


Keywords: 3.1i, Coregen, Virtex, dual port, block RAM, output, unknown,
VHDL, simulation, core generator

Urgency: Standard

General Description:
When performing a behavioral simulation of the CORE Generator Dual Port
Block RAM core for Virtex, the RAM outputs are unknown at the start of the
simulation. (This is despite the fact that the contents of the RAM are set to
valid initial values and all the input signals are at known levels.) When the
RAM is exercised (i.e., a read or write is performed), the output seems to
display valid data.


This has been known to happen when the signal feeding the clock port
of the RAM is initialized to logic level '1' (first transition is high -> low).

The workaround for this problem is to set the initial value of the clock
signal to '0' (so the first transition becomes low -> high).
AR# 10330
Date Created 10/16/2000
Last Updated 08/23/2002
Status Archive
Type General Article