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AR# 10349

1.1 System Generator for DSP - Multiplexor (MUX) with latency greater than 0 results in an EDIF error in implementation


Keywords: Sysgen, Mathworks, Simulink, simulation, multiplexor

Urgency: Standard

General Description:
Using a System Generator Block Multiplexor (MUX) with latency greater than 0
creates VHDL which, after synthesis, causes an EDIF error in the implementation


A workaround is to use the MUX with latency 0, and add delay elements in the
design (if you need latency) after the MUX.
AR# 10349
Date Created 10/18/2000
Last Updated 06/22/2004
Status Archive
Type General Article