Can I implement VREF with a voltage divider? Is there a current specification that should be followed?
Xilinx recommends to always separate VTT from VREF because the VTT supply is very noisy. A stable VREF using a small LDO is the desirable implementation.
A voltage divider implementation is possible. Knowledge of the PCB environment (that is, frequency of coupled noise) is required to correctly calculate the details (resistance and capacitance values) of the divider circuit.
As a result, an isolated reference supply is usually a more robust and simpler approach.