UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 10363

WebPACK 3.1i XST - Pin locks are not picked up correctly or are in the wrong order when "pin_assign" attribute is used

Description


General Description:

When I use the "pin_assign" attribute in VHDL on a range of pins, the software appears to ignore the constraints and places the pins in arbitrary locations.

Solution


This was fixed in the 4.1i software.



The following work-around can be used for earlier software versions:



Check to see if the bus is a non-standard range [e.g., (15 downto 8)], for an 8-bit bus. If so, you have two options:



1. Change the port definition so that it is (7 downto 0).



or



2. Add 8 "dummy" pins for the non-existent lower 8 bits. These pin constraints will not be used; only the last 8 will be.



For example:



attribute pin_assign of AH: signal is "p1 p1 p1 p1 p1 p1 p1 p1 p23 p22 p21 p20 p19 p18 p16 p14";
AR# 10363
Date Created 08/29/2007
Last Updated 07/09/2010
Status Archive
Type General Article