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AR# 10397

LogiCORE PCI - Tval (CLK to Signal Valid) PCI Requirment does not seem to be met in the Xilinx Timing Report


General Description: 

The Timing Analyzer generates a timing report with a section that  

shows the Clock to Pad values for the PCI design. The values 

that are reported do not meet the Tval (CLK to Signal Valid) delay  

requirements in the PCI specification.


The Xilinx PCI LogiCORE uses Address/Data Stepping. This  

allows an agent to enable its output drivers over several clock 

cycles. More information regarding Address/Data Stepping can 

be found in section 3.6.3 of the PCI Local Bus Specification,  

Revision 2.2. 


The timing report will only report the higher of  

the two following values: 

1. T Input to valid data on PAD 

2. Clock to valid data on PAD 


These two paths are illustrated in the following figure. 


PCI Data Bus Output Paths
PCI Data Bus Output Paths


The "T input to valid data on PAD" path will always  

be greater than the "Clock to valid data on PAD" 

because the Xilinx PCI LogiCORE uses Address/Data 

Stepping as defined by the PCI Local Bus Specification. 


The logic that controls the enable on the output buffer 

is constrained to several times the Tval (CLK to Signal  

Valid) value defined in the PCI Specification.

AR# 10397
Date Created 08/29/2007
Last Updated 05/14/2014
Status Archive
Type General Article