We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 10419

3.x FPGA Express - Warning: Cannot link to cell "cell_name" to its reference design "component_name". (FPGA-LINK-2) --OBUFTs


Keywords: cannot, link, cell, reference, design, warning, fpga, 2

Urgency: Standard

General Description:
When instantiating OBUFTs in CPLDs, you may recieve the following warnings from
FPGA Express:

"Warning: Cannot link cell 'component_name' to its reference design 'OBUFT'. (FPGA-LINK-2)"

"Warning: The cell 'component_name' is not linked to any design. (FPGA-CHECK-4)"

(where 'component_name' is the instantiated name of OBUFT.)


FPGA Express does not recognize OBUFT as a CPLD primitive. The workaround
is to instantiate an OBUFE and invert the enable line.

Component declaration template:

component OBUFE
port (E : in std_logic;
I : in std_logic;
O : out std_logic);
end component;

Module declaration template:

module OBUFE (E, I, O);
input E, I;
output O;
AR# 10419
Date Created 11/01/2000
Last Updated 08/11/2003
Status Archive
Type General Article