UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 1045

Foundation Simulator - XC7300/XC9500 flip-flop outputs are unknown (PRLD signal)

Description

Keywords: outputs, flip-flop, undefined, state, CPLD, timing simulation

Urgency: Standard

General Description:
When performing a Timing Simulation on a CPLD design, flip-flops outputs go into
undefined states, even though the Functional Simulation was successful.

The Foundation Simulator does not toggle the PRLD signal during the Power-on/
Reset initialization; the PRLD signal is present in the post-fitted netlist, so if this
signal is not toggled at the beginning of the simulation, the flip-flops are will not be
properly initialized.

Solution

At the beginning of the simulation, toggle the PRLD signal.

Add the signal "PRLD" to the Waveform Viewer Window. PRLD is active-high, so
drive it high, then low, at the start of the simulation to initialize all the flip-flops.

The PRLD signal should be toggled automatically in Foundation Logic Simulator
versions 1.5 and later.
AR# 1045
Date Created 06/06/1996
Last Updated 04/23/2001
Status Archive
Type General Article