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AR# 10482

ModelSim (MTI), COREGen - Macro 'BLOCK_ROM' (or 'SINE_AND_COSINE', 'DIST_ROM') is undefined.


Keywords: ModelSim, Verilog, MTI, COREGen, vlog, xilinxcorelib,
compile, block, rom, sine, cosine, macro, undefined, syntax, error, c_dds

Urgency: Standard

General Description:
When compiling the COREGen Verilog behavioral library in ModelSim,
the following errors occur:

# WARNING[10]: D:/XilinxCoreLib/C_DDS_V2_0.v(54): Macro
`BLOCK_ROM is undefined

# ERROR: D:/XilinxCoreLib/C_DDS_V2_0.v(54): near ";":syntax error

# WARNING[10]: D:/XilinxCoreLib/C_DDS_V2_0.v(57): Macro `SINE_AND_COSINE is undefined

# ERROR: D:/XilinxCoreLib/C_DDS_V2_0.v(57): near ";":syntax error

# WARNING[10]: D:/XilinxCoreLib/C_DDS_V2_0.v(67): Macro
`BLOCK_ROM is undefined

# ERROR: D:/XilinxCoreLib/C_DDS_V2_0.v(67): near ")":syntax error

# WARNING[10]: D:/XilinxCoreLib/C_DDS_V2_0.v(72): Macro
`DIST_ROM is undefined

# ERROR: D:/XilinxCoreLib/C_DDS_V2_0.v(72): near ")":syntax error


Make sure the "vlog" command includes the +incdir+ flag, as
described in Resolution 3 of (Xilinx Solution 8066).
AR# 10482
Date Created 08/29/2007
Last Updated 08/22/2003
Status Archive