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AR# 10492

6.0 Synplify Pro - When trying to use an AND gate with an input of '1' to model a buffer, it is optimized out.


Keywords: Synplify, Synplicity, AND, gate, buffer, optimized

Urgency: Low

General Description:
If a user creates a design that targets a 9500 device and wishes to use a two-input AND
gate with one input tied high, Synplicity will optimize the AND gate out, even if there are
syn_keep attributes on both sides of the AND gate.



A work-around is to, rather than using an AND gate, instantiate a BUF and put the
syn_keep attribute on both sides of the BUF.


Another work-around is to introduce a signal named "one" and preserve it as follows:

library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
use ieee.std_logic_arith.all ;
library synplify;
use synplify.attributes.all;

entity delay is
port (
data_in_MOST: in std_logic ;
delay_out: out std_logic_vector (24 downto 0);
bus_in: in std_logic
) ;
end delay ;

architecture delay_arch of delay is
signal one : std_logic;
signal delay_out_int: std_logic_vector (24 downto 0);

attribute syn_keep of delay_out_int : signal is true;
attribute syn_preserve of delay_out_int: signal is true;
attribute syn_keep of one: signal is true;
one <= '1';
delay_out_int(0) <= data_in_MOST;
delay_out_int(1) <= delay_out_int(0) and bus_in;

process (delay_out_int)
for i in 2 to 24 loop
delay_out_int(i) <= delay_out_int(i-1) and one;
end loop ;
end process;

delay_out (24 downto 0) <= delay_out_int (24 downto 0);

end delay_arch;
AR# 10492
Date Created 11/10/2000
Last Updated 04/20/2007
Status Archive
Type General Article