We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Page Bookmarked

AR# 10494

6.3i CORE Generator, Asynchronous FIFO, FIFO Generator - Behavioral and back-annotated simulation do not match


General Description:

The back-annotated simulation of the asynchronous FIFO behaves differently than the behavioral model simulation.

In an instance where the simulation of the asynchronous FIFO has the asynchronous clock inputs (rd_clk and wr_clk are at different speed), the back-annotated simulation might not exactly match the behavior of the supplied behavioral models.

Particularly, the state of status flags (full, empty, almost_full, almost_empty, rd_count and wr_count) might lead to lag changes that occur in the behavioral model.


The behavior of the back-annotated simulation is correct, despite the timing differences. If the interface logic is responding properly to the status information, especially "full" and "empty," the FIFO will behave correctly. The simulation differences are unavoidable because of the modeling of the routing delay in the asynchronous paths.

The asynchronous FIFO is designed to handle these asynchronous conditions, but because of the unpredictable routing delay, there is no way to make the behavioral model replicate the real conditions exactly.

If you need to simulate more of realistic behavior of Async FIFO, use the back-annotated simulation (post-ngdbuild or post-par). To generate post-PAR simulation model, run a netgen command on the routed design (NCD file). To generate post-ngdbuild simulation model, run:

1. ngdbuild my_fifo.edn

2. netgen -ofmt verilog my_fifo.ngd


netgen -ofmt vhdl my_fifo.ngd

AR# 10494
Date 12/15/2012
Status Active
Type General Article