We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 10572

3.1i XST - XST rejects a valid Verilog operator % (VLG__2008).


Keywords: %, operator, Verilog, power, 2

Urgency: Standard

General Description:
XST rejects a design, reporting the following error:

"ERROR: (VLG__2008). "filename.v", line ##:"

(Operator % is only supported when the second operand is a power of 2.)


This problem is fixed in the latest 3.1i Service Pack, available at:
The first service pack containing the fix is 3.1i Service Pack 6.
AR# 10572
Date Created 12/01/2000
Last Updated 08/19/2002
Status Archive
Type General Article