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AR# 10573

3.1i XST - VERILOG synthesis: XST hangs at 50% when synthesizing a Verilog file.

Description

Keywords: hang, Verilog, CPLD

Urgency: Standard

General Description:
XST has been seen to hang at 50% when synthesizing for CPLDs.

Solution

This problem is fixed in the latest 3.1i Service Pack available at:
http://support.xilinx.com/support/techsup/sw_updates. The first
service pack containing the fix is 3.1i Service Pack 6.
AR# 10573
Date Created 12/01/2000
Last Updated 08/19/2002
Status Archive
Type General Article