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AR# 10579

3.1i XFLOW - How do I allow XFLOW to invoke XST to synthesize HDL designs?

Description


General Description:

A hidden command line switch was added in 3.1i XFLOW to include XST synthesis in the design flow for PC users with Foundation ISE. The hidden switch, "-synth", allows XFLOW to invoke XST to synthesize HDL designs.



The following three resolutions document the steps for:



- Compiling for Functional Simulation (FPGA or CPLD)

- Implementing an FPGA Design

- Fitting a CPLD Design

Solution


COMPILING FOR FUNCTIONAL SIMULATION (FPGA or CPLD)



1. Create a single top-level design file that lists all your HDL source files.



XFLOW can accept only one input design file. If your HDL design does not contain multiple HDL source files, you may skip this step and use your single HDL source file as the input to XFLOW. Otherwise, you must create a top-level file to use as the input design file for XFLOW.



For Verilog designs, this is accomplished by creating a top-level Verilog file (e.g., "top.v") that lists all the Verilog source files using the `include construct:



`include "hdl_source1.v"

`include "hdl_source2.v"

...

`include "hdl_sourceN.v"



For VHDL designs, this is accomplished by creating a top-level project file (e.g., "top.prj") that lists all the VHDL source files with complete path names:



C:\source_files\hdl_source1.vhd

C:\source_files\hdl_source2.vhd

...

C:\source_files\hdl_sourceN.vhd



NOTE: If the "nosort" option is added to the end of the project file, the VHDL source files must be listed in the correct compilation order.



NOTE: For the remainder of this resolution, it is assumed that "top.v" is the top level input design file.



2. Enable XST in the FSIM.FLW file.



The FSIM.FLW file contains a program block for XST. The program block is disabled and commented out using "#" symbols. To enable the XST program block, delete the leading "#" symbols on the lines for the XST program block.



We recommend that you edit a copy of the FSIM.FLW file in your project directory, rather than the one located in the $XILINX installed area. You can copy the FSIM.FLW file into your project directory by running XFLOW with the "-norun" option:



XFLOW -p <parttype> -fsim <simulation_options>.opt -synth <synthesis_options>.opt -norun top.v



Possible choices for <synthesis_options>.opt are:



verilog_area.opt

verilog_speed.opt

vhdl_area.opt

vhdl_speed.opt



Possible choices for <simulation_options>.opt are listed in the 3.1i Development System Reference Guide:

http://toolbox.xilinx.com/docsan/3_1i/


See the XFLOW Chapter -> Flow Types -> -fsim



Once you have a copy of FSIM.FLW, edit it and delete the "#" symbols on the XST program block to enable XST in the flow:



# Flow Info for XST

#

Program xst

Flag: ENABLED;

Input: <synthdesign>;

Triggers: <design>.cst;

Exports: <design>.edn;

End Program xst



3. Run XFLOW to compile design for Functional Simulation.



XFLOW -p <parttype> -fsim <simulation_options>.opt -synth <synthesis_options>.opt top.v



NOTE: When using the "-synth" switch in XFLOW, you must specify the target part type on the command line using the "-p" switch.



IMPLEMENTING AN FPGA DESIGN



1. Create a single top-level design file that lists all your HDL source files.



XFLOW can accept only one input design file. If your HDL design does not contain multiple HDL source files, you may skip this step and use your single HDL source file as the input to XFLOW. Otherwise, you must create a top-level file to use as the input design file for XFLOW.



For Verilog designs, this is accomplished by creating a top-level Verilog file (e.g., "top.v") that lists all the Verilog source files using the `include construct:



`include "hdl_source1.v"

`include "hdl_source2.v"

...

`include "hdl_sourceN.v"



For VHDL designs, this is accomplished by creating a top-level project file (e.g., "top.prj") that lists all the VHDL source files with complete path names:



C:\source_files\hdl_source1.vhd

C:\source_files\hdl_source2.vhd

...

C:\source_files\hdl_sourceN.vhd



NOTE: If the "nosort" option is added to the end of the project file, then the VHDL source files must be listed in the correct compilation order.



NOTE: For the remainder of this resolution, it is assumed that "top.v" is the top level input design file.



2. Enable XST in the FPGA.FLW file.



The FPGA.FLW file contains a program block for XST. The program block is disabled and commented out using "#" symbols. To enable the XST program block, delete the leading "#" symbols on the lines for the XST program block.



We recommend that you edit a copy of the FPGA.FLW file in your project directory, rather than the one located in the $XILINX installed area. You can copy the FPGA.FLW file into your project directory by running XFLOW with the "-norun" option:



XFLOW -p <parttype> -implement <implement_options>.opt -synth <synthesis_options>.opt -norun top.v



Possible choices for <synthesis_options>.opt are:



verilog_area.opt

verilog_speed.opt

vhdl_area.opt

vhdl_speed.opt



Possible choices for <implement_options>.opt are listed in the 3.1i Development System Reference Guide:

http://toolbox.xilinx.com/docsan/3_1i/


See the XFLOW Chapter -> Flow Types -> -implement



Once you have a copy of FPGA.FLW in your project directory, edit it and delete the "#" symbols on the XST program block to enable XST in the flow:



#

# Flow Info for XST

#

Program xst

Flag: ENABLED;

Input: <synthdesign>;

Triggers: <design>.cst;

Exports: <design>.edn;

End Program xst



3. Run XFLOW to compile design for Functional Simulation



XFLOW -p <parttype> -implement <implement_options>.opt -synth <synthesis_options>.opt top.v



NOTE: When using the "-synth" switch in XFLOW, you must specify the target part type on the command line using the "-p" switch.



FITTING A CPLD DESIGN



1. Create a single top-level design file that lists all your HDL source files.



XFLOW can accept only one input design file. If your HDL design does not contain multiple HDL source files, you may skip this step and use your single HDL source file as the input to XFLOW. Otherwise, you must create a top-level file to use as the input design file for XFLOW.



For Verilog designs, this is accomplished by creating a top-level Verilog file (e.g., "top.v") that lists all the Verilog source files using the `include construct:



`include "hdl_source1.v"

`include "hdl_source2.v"

...

`include "hdl_sourceN.v"



For VHDL designs, this is accomplished by creating a top-level project file (e.g., "top.prj") that lists all the VHDL source files with complete path names:



C:\source_files\hdl_source1.vhd

C:\source_files\hdl_source2.vhd

...

C:\source_files\hdl_sourceN.vhd



NOTE: If the "nosort" option is added to the end of the project file, then the VHDL source files must be listed in the correct compilation order.



NOTE: For the remainder of this resolution, it is assumed that "top.v" is the top level input design file.



2. Enable XST in the CPLD.FLW file.



The CPLD.FLW file contains a program block for XST. The program block is disabled and commented out using "#" symbols. To enable the XST program block, delete the leading "#" symbols on the lines for the XST program block.



We recommend that you edit a copy of the CPLD.FLW file in your project directory, rather than the one located in the $XILINX installed area. You can copy the CPLD.FLW file into your project directory by running XFLOW with the "-norun" option:



XFLOW -p <parttype> -fit <fit_options>.opt -synth <synthesis_options>.opt -norun top.v



Possible choices for <synthesis_options>.opt are:



verilog_area.opt

verilog_speed.opt

vhdl_area.opt

vhdl_speed.opt



Possible choices for <fit_options>.opt are listed in the 3.1i Development System Reference Guide:

http://toolbox.xilinx.com/docsan/3_1i/


See the XFLOW Chapter -> Flow Types -> -fit



Once you have a copy of CPLD.FLW in your project directory, edit it and delete the "#" symbols on the XST program block to enable XST in the flow:



#

# Flow Info for XST

#

Program xst

Flag: ENABLED;

Input: <synthdesign>;

Triggers: <design>.cst;

Exports: <design>.edn;

End Program xst



3. Run XFLOW to fit design into a CPLD



XFLOW -p <parttype> -fit <fit_options>.opt -synth <synthesis_options>.opt top.v



NOTE: When using the "-synth" switch in XFLOW, you must specify the target part type on the command line using the "-p" switch.
AR# 10579
Date Created 08/29/2007
Last Updated 04/12/2012
Status Archive
Type General Article