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AR# 10641

3.3i Foundation ISE Project Importer - Unconnected pins are incorrectly exported

Description

Keywords: ISE, Project Navigator, XST, Express

Urgency: Standard

General Description:
If pins on a symbol are left unconnected on a schematic, the VHDL that is exported from Foundation shows these input pins as being connected to "Z." When this is applied to inputs, errors appear in synthesis.

Solution

Synthesis/Simulation tools require that inputs to components be defined. These "unconnected" pins must be assigned to signals or values either in the schematic, or through modification of the resulting VHDL files. If "dummy" signals are used, they will be optimized away by FPGA Express and connected to ground.

This would result in incorrect levels for pins, such as CE (Clock Enable) and other pins, that should be at logic level "high." These types of pins should be tied "high," either by tying them to VCC in the schematic, or by assigning the signal to |1| in HDL code.
AR# 10641
Date Created 08/29/2007
Last Updated 10/23/2003
Status Archive
Type ??????