UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 10642

3.3i Foundation ISE Project Importer - Schematics containing similar bus and pin names cause synthesis errors

Description

Keywords: ISE, Project Navigator, Project Importer

Urgency: Standard

General Description:
If a bus pin on a schematic symbol and a single net pin on the same
symbol have the same root name, a problem occurs when the VHDL
netlist is generated from the schematic, and synthesis will fail.

Example: A symbol with bus pin "c[7:0]" and clock pin is simply named
"c." This works successfully through schematic flow, but the VHDL
netlist will cause an error.

Solution

The signal pin or bus pin must be renamed. This can be done in
the schematic, or in the resulting VHDL structural netlist
AR# 10642
Date Created 12/14/2000
Last Updated 10/21/2002
Status Archive
Type General Article