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AR# 10651

ModelSim (MXE, SE, PE) - How do I specify the SDF file for timing simulation? (VHDL, Verilog)


Keywords: ModelSim, MXE, MTI, timing, back-annotated, simulation, SDF, VHDL, Verilog

Urgency: Standard

General Description:
How do I specify the SDF file for timing simulation?


Running Simulation from Project Navigator (VHDL or Verilog)

When running a simulation from ProjNav, ProjNav creates a "do" file that automatically specifies the SDF whenever you run the Simulate Post-Place & Route process.

For information on how to run simulation from ProjNav, please see (Xilinx Answer 18216).

Verilog - Running MTI Standalone
For Verilog, the timing simulation netlist has a "$sdf_annotate" statement that calls the SDF file. Therefore the SDF file will automatically be pulled in when loading the simulation.

VHDL - Running MTI Standalone
For VHDL, the SDF file must be specified through the MTI GUI or in the VSIM command line.

You must supply MTI with two pieces of information:
1. The region where the SDF file should be applied. The region tells MTI where the timing simulation netlist generated by the Xilinx tools is instantiated. Assume that the entity name in your testbench is TESTBENCH and the simulation netlist is instantiated inside the testbench with an instance name of UUT. The region for this example would be /TESTBENCH/UUT.
2. The location of the SDF file. If the SDF file is located in the same directory as the simulation netlist, you can just supply the name of the SDF file. Otherwise, the entire path to the SDF file must be specified.

Below is an example of the VSIM command line:
vsim -t ps -sdfmax /testbench/uut=c:/project/sim/time_sim.sdf work.testbench

For more information on how to run timing simulation using ModelSim, please see (Xilinx Answer 10177).
AR# 10651
Date Created 12/15/2000
Last Updated 11/23/2003
Status Active
Type General Article