UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 10652

CORE Generator IP 3.1isp6 3_IP2 - Virtex-II RPMed 16x14 Distributed RAM

Description


core, viewer







General Description:

I am generating a 16x14 dual-port Distributed RAM (Distributed Memory v3) for

a Virtex II device, and I have it RPMed. This should fit into 14 slices; instead,

only 1 LUT is used per slice, and it maps to 28 slices.

Solution


This problem is fixed in Distributed Memory v4_0 (D_IP3), which is scheduled

to be released on March 9, 2001.
AR# 10652
Date Created 08/29/2007
Last Updated 07/28/2010
Status Archive
Type General Article