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AR# 10715

Aldec Active HDL 4.1 - Problems compiling prims_utils_v3_0 in the XilinxCoreLib (IP2).


General Description:

I am compiling the VHDL module prims_utils_v3_0.vhd into the XilinxCoreLib library in Active HDL 4.1. V1 and v2 of the prims compile successfully, but the third prims fails with an error.


The problem is caused by a bug in the Aldec HDL simulator. Aldec reports that the bug will be fixed in the next service pack.

Meanwhile, avoid this problem by moving the "use" library clauses outside the package and package body.

Problems with the way the prims_utils_v3_0 file is written have been seen in the Aldec simulator (but not on any other platforms).

To correct the problems for Aldec only:

Change lines 279, 289, and 299 in prims_utils_v3_0.vhd, as shown below:

Change the line:

stack(stacki-1) := stack(stacki-1) and stack(stacki);


stack(stacki-1) := ieee.std_logic_1164."and"(stack(stacki-1),stack(stacki));

Change the line:

stack(stacki-1) := stack(stacki-1) or stack(stacki);


stack(stacki-1) := ieee.std_logic_1164."or"(stack(stacki-1),stack(stacki));

Change the line:

stack(stacki-1) := stack(stacki-1) xor stack(stacki);


stack(stacki-1) := ieee.std_logic_1164."xor"(stack(stacki-1),stack(stacki));

These changes will let the simulator use the function from the proper library, and are according to LRM (VHDL standard). (This is not a software problem.)

Then, recompile these three files. Ensure that this library is R/W.

The library will be updated and ready to use.
AR# 10715
Date Created 08/29/2007
Last Updated 07/28/2010
Status Archive
Type General Article