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AR# 10728

EXEMPLAR - How do I infer Virtex dual-port Block RAM in VHDL or Verilog?

Description

Keywords: Exemplar, dual, port, RAM, Virtex, Leonardo, Spectrum

Urgency: Standard

General Description:
Begining with Leonardo Spectrum version 2001.1d, it is now possible to infer dual-port RAM for the Virtex Architecture.

The 2 general cases listed below will infer dual-port Block RAM that will write to port DIA and read from port DOB:

NOTE: The port names are based on the the Block-RAM port names found in the Libraries Guide (Xilinx Manual "Libraries Guide", page 604).

Solution

1

CASE 1:

1. The read is synchronous.
2. There are 2 clocks.
3. There are 2 addresses.

NOTE: To turn off Block RAM inference, set the block_ram attribute to false. (This attribute is true by default, so it does not need to be added to infer Block RAM.)

VHDL Example:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity dualport_ram is
port (clka : in std_logic;
clkb : in std_logic;
wea : in std_logic;
addra : in std_logic_vector(4 downto 0);
addrb : in std_logic_vector(4 downto 0);
dia : in std_logic_vector(3 downto 0);
dob : out std_logic_vector(3 downto 0));
end dualport_ram;

architecture dualport_ram_arch of dualport_ram is
type ram_type is array (31 downto 0) of std_logic_vector (3 downto 0);
signal ram : ram_type;

attribute block_ram : boolean;
attribute block_ram of RAM : signal is TRUE;

begin

write: process (clka)
begin
if (clka'event and clka = '1') then
if (wea = '1') then
ram(conv_integer(addra)) <= dia;
end if;
end if;
end process write;

read: process (clkb)
begin
if (clkb'event and clkb = '1') then
dob <= ram(conv_integer(addrb));
end if;
end process read;

end dualport_ram_arch;

Verilog Example:

module dualport_ram (clka, clkb, wea, addra, addrb, dia, dob);
input clka, clkb, wea;
input [4:0] addra, addrb;
input [3:0] dia;
output [3:0] dob;

reg [3:0] ram [31:0];
reg [4:0] read_dpra;
reg [3:0] dob;

// exemplar attribute ram block_ram TRUE

always @ (posedge clka)
begin
if (wea) ram[addra] = dia;
end

always @ (posedge clkb)
begin
dob = ram[addrb];
end

endmodule // dualport_ram

2

CASE 2:

1. The read is synchronous.
2. There is 1 clock.
3. There are 2 addresses.

NOTE: To turn off Block RAM inference set the block_ram attribute to false. (This attribute is true by default so it does not need to be added to infer Block RAM.)

VHDL Example:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity dualport_ram is
port (clk : in std_logic;
wea : in std_logic;
addra : in std_logic_vector(4 downto 0);
addrb : in std_logic_vector(4 downto 0);
dia : in std_logic_vector(3 downto 0);
dob : out std_logic_vector(3 downto 0));
end dualport_ram;

architecture dualport_ram_arch of dualport_ram is
type ram_type is array (31 downto 0) of std_logic_vector (3 downto 0);
signal ram : ram_type;

attribute block_ram : boolean;
attribute block_ram of ram : signal is TRUE;

begin

process (clk)
begin
if (clk'event and clk = '1') then
if (wea = '1') then
ram(conv_integer(addra)) <= dia;
end if;
dob <= ram(conv_integer(addrb));
end if;
end process;

end dualport_ram_arch;

Verilog Example:

module dualport_ram (clk, wea, addra, addrb, dia, dob);
input clk, wea;
input [4:0] addra, addrb;
input [3:0] dia;
output [3:0] dob;

reg [3:0] ram [31:0];
reg [4:0] read_dpra;
reg [3:0] dob;

// exemplar attribute ram block_ram TRUE

always @ (posedge clk)
begin
if (wea) ram[addra] = dia;
dob = ram[addrb];
end

endmodule // dualport_ram
AR# 10728
Date Created 08/29/2007
Last Updated 04/20/2007
Status Archive
Type General Article