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AR# 10735

3.1i COREGEN, D_IP2 - Virtex Synchronous FIFO V1_0 Core Description is invalid


Keywords: 3.1i, CORE Generator, COREGEN, D_IP2, Virtex, synchronous, FIFO, RAM, core,
description, SelectRAM+, Distributed RAM

Urgency: Standard

General Description:
The Core Description (inside CORE Generator) states that it is possible to place the
Virtex Synchronous FIFO core in either SelectRAM+ or in Distributed RAM. However,
there is no option to choose which kind of RAM to implement.


This is an error in the Core Description for the Synchronous FIFO v1_0; this version
of the core only supports Distributed RAM type.

The new version (v2_0) of Synchronous FIFO that will be released with 3.1i IP
Update # 3 will have an option to implement RAM using either the Distributed
RAM (SRL16) or SelectRAM+(Block RAM).
AR# 10735
Date Created 01/07/2001
Last Updated 08/23/2002
Status Archive
Type General Article