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AR# 10807

3.1i Logic Simulator - Virtex Block RAM - "Signal: dpram.CLKA too short setup time. Missing Time: 3.9ns"


Keywords: F3.1i, timing, block RAM, short, setup, time, missing, 3.9nS, CLKA, CLKB

Urgency: Standard

General Description:
When a timing simulation of Virtex (or Spartan II) Block RAM is performed using
F3.1i with any service pack, the following timing violation occurs if both CLKA
and CLKB are driven by the same clock:

<design name>.CLKA -- too short setup time, missing time 3.9ns.
<design name>.CLKB -- too short setup time, missing time 3.9ns.

This message occurs even if the A and B addresses are different.



The Foundation Logic Simulator is incorrectly handling the SUCLKAHICLKB
and SUCLKBHICLKA parameters; these should only apply if the two addresses
are the same.

The current methods for working around this problem are to:

1. Edit the EDIF file, and change the parameter values to "0." This option allows
other timing violations to be found and stops the simulation; however, the EDIF file
would have to be edited for every new iteration of the design.

2. After the simulation stops the for the first time due to this false violation, select the
Ignore option. The simulator will then continue without displaying the message again.

3. Edit the simulator preferences to not report timing violations ("display but not register").
To do this:

- Open Logic Simulator
- Click on Options->Preferences
- Select the Reports tab
- On the Timing Violations line, deselect "Register" (leave "Display" and "Report"

This option prevents the violations from stopping the simulation, but still reports them
with all other timing violations in the console and Aldec.log file.


This error is scheduled to be fixed with the next major software release.
AR# 10807
Date Created 01/17/2001
Last Updated 08/15/2002
Status Archive
Type General Article