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AR# 10827

4.1i WebPACK - How do I perform timing simulation on an ABEL design?

Description

Keywords: WebPACK, timing, simulation, ABEL

Urgency: Standard

General Description:
How do I perform timing simulation on an ABEL design using WebPACK ISE? ABEL allows
for functional test vectors that ModelSim doesn't understand, and HDL Bencher doesn't
understand ABEL as an input file. What can be done?

Solution

1. In Implementation Options (Implement Design -> Properties -> Timing Simulation tab),
produce a VHDL or Verilog timing simulation output.
2. Open HDL Bencher from the Windows Start-> Programs menu.
3. Load the time_sim.vhd or time_sim.v file into HDL Bencher.
4. Create your test waveforms in HDL Bencher, and export the time_sim_tb.v/vhd file.
5. Open ModelSim XE from the Windows Start -> Programs menu.
6. If using a VHDL flow, skip to instruction 7a.

6a. In the command line window of MXE, type cd /<project directory>. This should
be the directory containing the time_sim.v and time_sim_tb.v files.
6b. Type> vlib work.
6c. Type> vmap work "./work" .
6d. Type> vlog time_sim.v.
6e. Type> vlog time_sim_tb.v .
6f. Type> vsim testbench .
6g. Go to View->Signals, and select the signals you wish to view.
6h. Type> run 1us (or however long the simulation needs to run)
- end Verilog simulation flow -

7a. In the command line window of MXE, type cd /<project directory>. This should
be the directory containing the time_sim.vhd and time_sim_tb.vhd files.
7b. Type> vlib work .
7c. Type> vmap work "./work".
7d. Type> vcom time_sim.vhd.
7e. Type> vcom time_sim_tb.vhd.
7f. Type> vsim testbench.
7g. Go to View -> Signals and select the signals you wish to view.
7h. Type> run 1us (or however long the simulation needs to run)
- end VHDL simulation flow -
AR# 10827
Date Created 01/19/2001
Last Updated 08/08/2003
Status Archive
Type General Article