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AR# 10853

3.1i COREGEN - 32i_ip_update2 contains duplicate files for blkmemsp_v3_0.v, blkmemdp_v3_0.v, and encode_8b10b_V1_0.pdf.

Description

Keywords: CORE Generator, COREGen, 32i_ip_update2, D_IP2, block memory, blkmemspv3_0.v ,
blkmemdp_v3_0.v, encoder

Urgency: Hot

General Description:
Problem 1
When running behavioral simulation for Single Port Block Memory v3_0, I encounter an
error/warning from the simulator regarding an incorrect number of parameters in the port list.

Problem 2
When running behavioral simulation for Dual Port Block Memory v3_0, I encounter "xxxx" on
the output port when trying to access the invalid address location.

Problem 3
When reading the data sheet for Encoder_8b10b v1_0, the title and the section headers are
illegible.

Problem Source
The original 32i_ip_update2.zip and 32i_ip_update2.tar.gz contain duplicate files. The file
names are the same, but one is written in lower-case letters and the other in upper-case.
The lower-case file is correct, and the capitalized file is not.


BLKMEMSP_V3_0.v 13kb 10/27/00 (wrong file)
blkmemsp_v3_0.v 14kb 11/07/00 (correct file)
BLKMEMDP_V3_0.v 32kb 10/27/00 (wrong file)
blkmemdp_v3_0.v 31kb 11/07/00 (correct file)

ENCODE_8B10B_V1_0.pdf 302kb 11/09/00 (correct file)
encode_8b10b_v1_0.pdf 301kb 11/09/00 (wrong file)

NOTE: In the IP update zip and tar files, the Verilog behavioral models reside in two
different directories:

1) ..\verilog\src\XilinxCoreLib\
2) ..\coregen\ip\xilinx\<core_name>\com\xilinx\ip\<core_name>\simulation\

The data sheet file <core_name>.pdf is supposed to reside in only one location:

..\coregen\ip\xilinx\<core_name>\com\xilinx\ip\<core_name>\doc\

Solution

1

For PC :

If you have already installed the original IP update, released in November, 2000:

32i_ip_update2.zip
http://www.xilinx.com/ipcenter/coregen/updates.htm#update

1. Remove the files below from your current Xilinx installation. Your Xilinx 3.1i software
is installed in <XILINX>. You may have only one file in each directory (either in upper-
or lower-case), but it is necessary to delete both of them.

<XILINX>\verilog\src\XilinxCoreLib\ BLKMEMDP_V3_0.v
<XILINX>\verilog\src\XilinxCoreLib\ blkmemdp_v3_0.v
<XILINX>\verilog\src\XilinxCoreLib\ BLKMEMSP_V3_0.v
<XILINX>\verilog\src\XilinxCoreLib\ blkmemsp_v3_0.v
<XILINX>\coregen\ip\xilinx\blkmemdp_v3_0\com\xilinx\ip\blkmemdp_v3_0\simulation\BLKMEMDP_V3_0.v
<XILINX>\coregen\ip\xilinx\blkmemdp_v3_0\com\xilinx\ip\blkmemdp_v3_0\simulation\blkmemdp_v3_0.v
<XILINX>\coregen\ip\xilinx\blkmemsp_v3_0\com\xilinx\ip\blkmemsp_v3_0\simulation\BLKMEMSP_V3_0.v
<XILINX>\coregen\ip\xilinx\blkmemsp_v3_0\com\xilinx\ip\blkmemsp_v3_0\simulation\blkmemsp_v3_0.v
<XILINX>\coregen\ip\xilinx\encode_8b10b_v1_0\com\xilinx\ip\encode_8b10b_v1_0\doc\ENCODE_8B10B_V1_0.pdf
<XILINX>\coregen\ip\xilinx\encode_8b10b_v1_0\com\xilinx\ip\encode_8b10b_v1_0\doc\encode_8b10b_v1_0.pdf

2. Download the newer update file:

32i_ip_update2a.zip
http://www.xilinx.com/ipcenter/coregen/updates.htm#update

3. Extract the newer update files into your current Xilinx installation, using the following
options:

- select "use folder names"
- select "verwrite existing files"

4. If you plan to perform behavioral simulation using the Verilog models provided in
<XILINX>\verilog\src\XilinxCoreLib, you may need to re-compile the following,
depending upon the simulator you are using:

blkmemdp_v3_0.v and
blkmemsp_v3_0.v

Using your Verilog simulator, you can either re-compile all the files in the XilinxCoreLib
directory, or just the two files listed above if you have already compiled the other files.

2

For UNIX systems:

Both the upper-case and lower-case files will be saved; therefore, it is not necessary to
install the newer update. Simply delete the incorrect files from appropriate directories:

BLKMEMSP_V3_0.v 13kb 10/27/00 (wrong file)
BLKMEMDP_V3_0.v 32kb 10/27/00 (wrong file)
encode_8b10b_v1_0.pdf 301kb 11/09/00 (wrong file)
AR# 10853
Date Created 01/25/2001
Last Updated 08/23/2002
Status Archive
Type General Article