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AR# 10867

3.1i Virtex-II PAR - PAR Warning: "Route:49 - The signal "GLOBAL_LOGIC0" has no loads so was not routed."

Description

Keywords: BitGen, PAR, router, unrouted, not routed, GLOBAL_LOGIC0, GLOBAL_LOGIC, WARNING:Route:49

Urgency: Standard

General Description:
My designs have PWR/GND signals with no loads, and as a result, the following messages are reported from BitGen DRC:

"WARNING:Route:49 - The signal "GLOBAL_LOGIC0" has no loads so was not routed."
or:
"WARNING:Route:49 - The signal "GLOBAL_LOGIC1" has no loads so was not routed."

Solution

1

This problem occurs because of pin swapping. When all load pins are swapped away from a PWR/GND net, PAR fails to remove the resulting loadless net.

This problem is fixed in the latest 3.1i Service Pack, available at:
http://support.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is 3.1i Service Pack 7.

NOTE: The SP7/SP8 fix for this problem may introduce a new problem in some designs that causes the timing score to diverge during routing. Please see (Xilinx Answer 11421) for further details.

2

This problem can be avoided in versions prior to SP7 and in SP8 if the patch for (Xilinx Answer 11421) is installed.

To work around this issue, you can disable DRC during BitGen by using the "-d" switch. Alternatively, you can use FPGA Editor to manually delete the loadless PWR/GND nets flagged by DRC. In version 4.1i, DRC will ignore these harmless nets by default.
AR# 10867
Date Created 08/29/2007
Last Updated 10/21/2008
Status Archive
Type General Article