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AR# 10901

6.1i FPGA Editor - How do I create a hard macro?

Description

Keywords: FPGA Editor, hard macro, 3.1i

Urgency: Standard

General Description:
How do I create a hard macro in the FPGA Editor?

Solution

1

To create a hard macro in the FPGA Editor, follow these steps:

1. After routing your design, open the "design.ncd" file in FPGA Editor.
2. Save your design as a macro with File -> Save As.
3. Place the FPGA Editor in "edit mode" with File -> Main Properties -> Edit Mode = Read Write.
4. Before this macro is ready for instantiation at a lower-level in your design, all of the pad components must be removed. To remove a pad, follow these steps:
a. Select the pad.
b. Go to Tools -> Place -> Unplace. This will un-place the pad component and un-route the signal to it.
5. A green dot appears over the pin on the slice that had previously been routed to that pad. Add an External Macro pin to this site; this will allow the pin to be instantiated in your code.

NOTES:
- If the IOB was routed to two pins on a slice, you must give both pins a different name or PAR will issue errors.
- If you have a net that drives both a SLICE and an IOB, and you remove the IOB, the route between slices will still be routed. Consequently, you must remember which SLICE.PIN drives your IOB.

To add an External Macro pin, perform the following:
a. Select the pin (from the net that was just un-routed).
b. Go to Edit -> Add Macro External Pin. The "External Name" is the port name that will be referenced in the instantiation.
6. To maintain the relative placement of the CLBs/Slices in the Macro, select a CLB to use as the reference, and go to Edit -> Set Macro Reference Comp. This effectively creates an RPM, and makes the system timing as consistent as possible.
7. Delete the un-placed pads and un-routed nets from your list window by selecting the un-placed or un-routed components in the list window and click the Delete button (located near the right side of the FPGA Editor window).
8. Instantiate the macro as you would any other component. The macro file name is the component name, and the External Macro Pin names that were added are the ports.

2

A good example of creating a hard macro can be found in (Xilinx XAPP123): "Using Three-State Enable Registers in XLA, XV, and Spartan-XL FPGAs."

3

Note that VCC comps are no longer supported in the 5.1i FPGA Editor and later when creating hard macros. To work around this issue, you can simply declare any pin that is fed by VCC as an external macro pin and connect the port to '1' when instantiating the macro in your source code.

4

Routed hard macros tend to cause longer run times in PAR, and might cause PAR to crash. If this occurs, unroute all routes as a work-around and open a WebCase at:
http://support.xilinx.com/support/clearexpress/websupport.htm
AR# 10901
Date Created 01/31/2001
Last Updated 03/13/2005
Status Active
Type General Article