.v line ####)"">
When I try to load a design for Verilog simulation, the following error is issued within VCS:
"Error: undefined hierarchical reference "glbl.GSR" (<design>.v line ####)"
This error is a result of the non-usage of the "glbl.v" module during the compilation and loading of the design. The "glbl.v" module enables the use of the global set/reset in the design, and it is referenced by the UNISIMS and the SIMPRIMS libraries. The "glbl.v" module at the following location, "$XILINX/verilog/src/glbl.v", and needs to be both compiled and loaded in the simulation process.
Please see (Xilinx Answer 5263) on how to run simulation using VCS.
For more details on the usage of the "glbl.v" module, see (Xilinx Answer 6537).