My design is targeted to a Virtex/Virtex-E device. I am attempting to delay startup until the DLL locks, using the Startup_wait property on the DLL.
However, this property is not allowing my device to configure. If I remove this property, my device configures correctly; however, if I use it, the device does not configure.
For a 1x clock:
This is a working start-up cycle configuration:
It is important to release GSR before the LCK_cycle. It is also important to release GTS before the LCK_cycle if external feedback is used. Failing to do so will keep the DLL from locking because the pin driving the external feedback clock will remain tri-stated and the DLL will never see the feedback clock.
To set the start-up options, edit the "bitgen.ut" file or set the options in the Project Navigator GUI.
In the Project Navigator GUI:
1. Right-click "Generate Programming File" -> Select "Properties."
2. Under the "Startup Options" tab:
Enable Outputs = GTS_cycle (C1)
Release GSR = GSR_cycle (C1)
Release DLL = LCK_cycle (C2)
Done = DONE_cycle (C4)
NOTE: Setting the GTS and GSR cycles before the DONE cycle might cause problems in daisy-chain applications.
For a 4x clock:
For the 4x clock, logic using the SRL16s is needed to implement it, so the GWE (global write enable) must be set before the LCK_cycle as well.