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AR# 11011

3.1i CPLD 9500/XL - Latches in CPLD hardware exhibit strange behavior when timing simulation passes.


Keywords: 9500, CPLD, latch, JEDEC, transparent

Urgency: Hot

General Description:
When using a latch in a 9500 design, the timing simulation is correct; however, on the device, the latch clears for no apparent reason.


Latches are often implemented by the fitter with the asynchronous clear and preset of a register. When the JEDEC generation occurs (Hprep6), the clock input of the register is erroneously connected to Global Clock Line 2. When this clock line toggles, the register clocks in a "0" because the data line to the register is unconnected -- this resets the flip-flop.

This problem is fixed in the latest 3.1i Service Pack, available at:
The first service pack containing the fix is 3.1i Service Pack 8.

Here are two work-arounds for this issue if you do not wish to get Service Pack 8:

Example Latch Equation:
Y = (/G and Y) or (G and D) or (D and Y)

Alternatively, you may route the Q output of the register back to the D input, thereby allowing the clocking to occur, but ensuring that the proper value is latched back.

AR# 11011
Date Created 02/16/2001
Last Updated 08/23/2002
Status Archive
Type General Article