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AR# 11024

3.1i CORE Generator - Multiplier v2_0 vhdl behavioral model (mult_gen_v2_0.vhd) causes "Illegal reference of signal" error during compilation.

Description

Keywords: CORE Generator, COREGen, multiplier, mult_gen, simulation, compile, Synopsys,
VSS, Cadence, NC-VHDL, Innoveda, Speedwave, IP update

Urgency: Standard

General Description
When trying to compile a CORE Generator simulation library (xilinxcorelib) with a simulator
other than ModelSim, the file mult_gen_v2_0.vhd may cause the following errors:

Synopsys VSS:
**Error: vhdlan,826 C:\Xilinx\vhdl\src\XilinxCoreLib\mult_gen_v2_0.vhd(505):
Can not read signal during static elaboration.

Cadence NC-VHDL:
ncvhdl: v3.00.(s15): (c) Copyright 1995 - 2000 Cadence Design Systems, Inc.
mult_gen_v2_0.vhd:
signal b_input : std_logic_vector((find_ccm_b_width(str_to_slv(c_b_value, c_b_width),
c_b_width, c_mult_type, c_has_loadb)-1) downto 0) := set_b_value(b); |
ncvhdl_p: *E,ILSGRD (mult_gen_v2_0.vhd,505|153): illegal reference of a signal (B) during
static elaboration [12.3].
signal bconst0 : std_logic_vector((find_ccm_b_width(str_to_slv(c_b_value, c_b_width),
c_b_width, c_mult_type, c_has_loadb)-1) downto 0) := set_b_value(b);

Innoveda Speedwave:
ERROR[495]::File mult_gen_v2_0.vhd Line 505: Illegal reference of signal - cannot
elaborate statically

Depending upon the simulator, the actual error messages may differ.

Solution

A work-around is to compile other files without mult_gen_v2_0.vhd; this allows other cores to be
compiled. If simulation of multiplier v2_0 is needed, post-NGDBuild simulation can be performed,
as described in (Xilinx Answer #8065).
AR# 11024
Date Created 02/20/2001
Last Updated 08/23/2002
Status Archive
Type General Article