5.1i XST - How do I use the INIT attribute to initialize a LUT?
Description
Keywords: INIT, LUT, syntax, XST
Urgency: Standard
General Description:
How do I use the INIT attribute to initialize a LUT?
Solution
1
For general information on how LUTs are initialized, please see the information regarding LUTs in the Libraries Guide at:http://support.xilinx.com/support/library.htm
Verilog Syntax:
module top (O, I0, I1, I2, I3);
input I0, I1, I2, I3;
output O;
LUT4 U1 (.O(O), .I0(I0), .I1(I1), .I2(I2), .I3(I3));
// synthesis attribute INIT of U1 is "8000"
endmodule
2
For general information on how LUTs are initialized, please see the information regarding LUTs in the Libraries Guide at:http://support.xilinx.com/support/library.htm
VHDL syntax
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity test is
port (
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
O : out std_logic);
end test;
architecture behavioral of test is
component LUT4
port (
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
O : out std_logic);
end component;
attribute INIT : string;
attribute INIT of u1 : label is "8000";
begin
u1 : LUT4 port map(I0 => I0, I1 => I1, I2 => I2, I3 => I3, O => O);
end behavioral;