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AR# 11087

3.1i CORE Generator - Known Issues in the 3.1i IP Update #3 (D_IP3)


Keywords: _IP3, 32i_ip_update3, release note, COREGen, DA, FIR, filter, sine, cosine, LUT, lookup, table, Virtex, adder, subtracter, FD, based, shift, register, accumulator, Virtex-II, block, RAM, memory, problem, single-port, dual-port, block memory, Asynchronous FIFO, release notes, distributor memory, FFT, 32i_ip_update_3, CORE Generator

Urgency: Standard

General Description:
This answer record addresses known issues in 32i_ip_update3 (also referred to as "D_IP3").



Software Compatibility

The D_IP3 IP update is only compatible with Xilinx CORE Generator v3.1i, which is included with Alliance v3.1i, Foundation v3.1i, and Foundation ISE v3.1i software. This IP update is also compatible with v3.2i , v3.3i, and subsequent releases. This IP update should not be used with any other versions of CORE Generator (such as v2.1i or earlier).

Service Pack Requirement

D_IP3 has been tested with Xilinx software v3.1i and Service Pack 7. The latest service pack for v3.1i is available at: http://support.xilinx.com/support/techsup/sw_updates/

Previous IP update Requirement

D_IP3 update is cumulative; therefore, previous IP updates are not required. If you are a Workstation user and have already installed 3.1i_ip_update1 (D_IP1) on your system, your system administrator may need to change the permissions on your current CORE Generator installation before you install the D_IP3 update. This can be done by using the following command:

chmod -R u+w $XILINX/coregen

Acrobat Reader Requirement

Acrobat Reader version 4 or later must be installed in order to view core data sheets correctly. Acrobat software can be downloaded from the following Adobe site:


Distributed Memory v4_0

1. When large Distributed Memory (C_DIST_MEM_V4_0) cores are generated, there is a possibility that the design will fail when it passes through BitGen. This failure occurs because PAR does not correctly insert buffers to signals that have very large fanouts. -- Please see (Xilinx Answer 11103).

2. The placer rejects valid Virtex-II DPRAM macros, including some defined by CORE Generator. The errors posted begin with the message:

v2_dpr_32X16_INST/hset" may not be placed in such a way that it can be routed."

Please see (Xilinx Answer 10505).

Multiplier v3_0

1. When using Xilinx CORE Generator Multiplier v3_0 with Type set to "sequential," the correct output result may not be given if the output width is less than the minimum required width. -- Please see (Xilinx Answer 10964).

2. When compiling Multiplier v3_0 VHDL behavioral model (mult_gen_v3_0.vhd) with simulators other than ModelSim (MTI), errors may occur during the compilation. -- Please see (Xilinx Answer 11161).

32-Point Parameterizeable FFT v1_0

A Verilog behavioral simulation model is NOT available for this core; however, CORE Generator will output a .veo (instantiation) file without any error/warning. -- Please see (Xilinx Answer 11155).

Direct Digital Synthesizer v3_0

When using the DDS v3.0, targeting a Virtex-II, and choosing to implement using block ROM, an error message may be reported when a core is generated. -- Please see (Xilinx Answer 11203).

Reed Solomon Decoder/Encoder v1_0

1. Starting CORE Generator after installing the D_IP3 update may cause the following errors:

"ERROR: Could not locate Project core xilinx_reed-solomon_decoder|xilinx|virtex+xc4000+spartan|1.0
ERROR: Could not locate Project core xilinx_reed-solomon_encoder|xilinx|virtex+xc4000+spartan|1.0"

These messages can be safely ignored. -- Please see (Xilinx Answer 11238).

2. The Xilinx Reed Solomon Encoder and Decoder that is currently available with 3.xi_ip_update3 is v1_0. The data sheet will indicate v2_0; however, the available core is v1_0, and it does not support Virtex-II architecture. -- Please see (Xilinx Answer 11239).
AR# 11087
Date Created 02/27/2001
Last Updated 08/23/2002
Status Archive
Type General Article