We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 11113

3.1i CPLD XC9500 Hitop - Illegal optimization causes inputs to be removed or incorrect logic to be implemented.


Keywords: Hitop, 9500, WebPACK, ISE, optimization

Urgency: Standard

General Description:
A CPLD 9500 design is being illegally optimized during Hitop. The design entry can be in schematic, VHDL, Verilog or ABEL.


The name of the entity or module -- and, hence, the name of the top-level netlist -- contains a keyword "NOR" in its name (e.g., "north_design").

This keyword is causing the tools to change the design's logic; thus, the optimization stage is then removing logic based on this altered design. This is reflected in the timing simulation.

A simple fix is to change the design name so that it does not contain the keyword (e.g., "Nbay").

This problem is fixed in the latest 3.1i Service Pack, available at:
The first service pack containing the fix is 3.1i Service Pack 8.
AR# 11113
Date Created 03/02/2001
Last Updated 08/23/2002
Status Archive
Type General Article