Description
Keywords: IFFT, CORE Generator, VEO, template, functional, LogiCORE, VSIM
I generate a FFT using the Verilog flow, and the VEO template file is created. However, I cannot find a Verilog simulation model. Why? Also, the following error occurs when I perform a Verilog behavioral simulation:
"Error: (vsim-3033) ... The design unit was not found"
Solution
The FFT does not have a Verilog behavioral model. The supported language for behavioral simulation is VHDL. If your simulator does not support multiple languages, you can work around this issue by generating a Verilog structural model with ISE 7.1i or above.
For more information, see
(Xilinx Answer 22333).
Please see
(Xilinx Answer 29209) for a detailed list of LogiCORE Fast Fourier Transform (FFT) Release Notes and Known Issues.