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AR# 11161

5.1i CORE Generator - The multiplier v3_0 VHDL behavioral model (mult_gen_v3_0.vhd) will not compile when NC-VHDL or other simulators are used

Description


General Description:

When I compile the multiplier v3_0 VHDL behavioral model (mult_gen_v3_0.vhd) with simulators other than ModelSim (MTI), the errors below are reported during the compilation. (The actual error messages will vary, depending upon the simulator.)



The following error is from Cadence NC-VHDL:



"ncvhdl: v3.20.(p1): (c) Copyright 1995 - 2000 Cadence Design Systems, Inc.

constant out_size : integer := find_ccm_out_width(b_input, c_baat+c_b_width, c_baat) ;

|

ncvhdl_p: *E,ILSGRD (mult_gen_v3_0.vhd,521|58): illegal reference of a signal (B_INPUT) during static elaboration [12.3].

signal full_out_size : integer := find_ccm_out_width(b_input, c_a_width+c_b_width, c_a_width) ;

|

ncvhdl_p: *E,ILSGRD (mult_gen_v3_0.vhd,523|61): illegal reference of a signal (B_INPUT) during static elaboration [12.3].

constant b_is_0 : boolean := b_input'length = 1 and b_input(0)='0' and c_mult_type = 2;

|

ncvhdl_p: *E,ILSGRD (mult_gen_v3_0.vhd,527|60): illegal reference of a signal (B_INPUT) during static elaboration [12.3]."



Unfortunately, at the time of this IP_Update release, the only simulator available was MTI, and this problem was not detected until after the release.

Solution


If hand-editing the behavioral model is not a good solution for you, another option is to compile your XilinxCoreLib without the mult_gen_v3_0.vhd file.



If simulation of Multiplier v3_0 is required, post-NGDBuild simulation can be performed as described in (Xilinx Answer 8065).



To work-around this problem, hand-edit the VHDL behavioral model for Multiplier v3_0 as follows:



1. Make a back-up of the following file before making any modifications:

<XILINX>/vhdl/src/XilinxCoreLib/mult_gen_v3_0.vhd



2. Open the above file using a text editor displays line number indicators.



3. Search for line #521:



constant out_size : integer := find_ccm_out_width(b_input , c_baat+c_b_width, c_baat);



Change "b_input" to "set_b_value". The line should read:



constant out_size : integer := find_ccm_out_width(set_b_value, c_baat+c_b_width, c_baat);



4. Search for line #523:



signal full_out_size : integer := find_ccm_out_width(b_input, c_a_width+c_b_width,c_a_width) ;



Change "b_input" to "set_b_value". The line should read:



signal full_out_size : integer := find_ccm_out_width(set_b_value, c_a_width+c_b_width,c_a_width) ;



5. Search for line #527:



constant b_is_0 : boolean := b_input'length = 1 and b_input(0)='0' and c_mult_type = 2;



Change b_input(0)='0' to set_b_value(0)='0'. The line should read:



constant b_is_0 : boolean := b_input'length = 1 and set_b_value(0)='0' and c_mult_type = 2;
AR# 11161
Date Created 08/29/2007
Last Updated 07/28/2010
Status Archive
Type General Article