We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 11245

3.1i Foundation ISE - VHDL user-defined packages are not being simulated.


Keywords: ISE, Project Navigator, packages, simulation

Urgency: Standard

General Description:
Why are VHDL user-defined packages not being simulated?


User-defined packages are not compiled by default for the ModelSim
processes, as the user is responsible for compiling these.

To do this, select the package in the Source window. In the Process
window, double-click on the "Compile for Simulation" process.

NOTE: This process must be rerun if "Delete Implementation Data" is run.
AR# 11245
Date Created 03/20/2001
Last Updated 05/04/2006
Status Archive
Type General Article